An important issue relating to nonvolatile memory devices, such as flash memory devices, regards the managing of internal circuit nodes of the memory devices in the periods subsequent to the occurrence of a sudden interruption in the supply voltage, for example, caused by a malfunctioning of the supply source. Typically, as soon as the supply voltage of a memory device becomes zero, all the signals driving and/or biasing the components of the memory device run out. As a consequence, the internal circuit nodes in turn lose bias, and discharge because of the “leakage effect”. The time spent by such nodes for completely discharging cannot be quantified beforehand, being based on the values of the sub-threshold currents of the transistors and on the conductivity of the discharge paths, which are parameters that strongly depend on the tolerances of the manufacturing process employed for producing the device.
If the supply voltage becomes zero while the memory device is carrying out an operation, such operation is interrupted, jeopardizing the correct outcome thereof. Moreover, if the operation interrupted by the extinction of the supply voltage involved the use of high voltages, for example programming or erasing voltages obtained by increasing the supply voltage through booster circuits such as charge pumps, the uncontrolled discharge from the leakage effect of the circuit nodes biased to such high voltages may cause the occurrence of irreversible structural damage in the memory device, compromising the correct operation thereof.
With, for example, reference to a modern memory flash device, during an erasing operation, and particularly during the generation of the erasing pulse, very high voltage differences are generated, for example on the order of 18 Volts. Furthermore, the wordlines of the memory sector subjected to erasing are biased with a high (in absolute value) negative voltage, for example −9 Volts, while the circuit nodes corresponding to the source regions, to the wells and to the buried layers are biased with a high positive voltage, for example 9 Volts. A standard erasing operation provides that, after the provision of the erasing pulse, the wordlines and the nodes corresponding to the source regions, the wells and the buried layer, are discharged to the reference voltage (ground) via two parallel discharge paths, one for the negative voltages and one for the positive voltages. If during the provision of the erasing pulse the supply voltage becomes zero, all of the circuits dedicated to the wordline discharge process and the abovementioned circuit nodes are not supplied anymore, with the result being that both the wordlines and such circuit nodes are left into a floating condition at high voltages compared to the ground voltage. The uncontrolled discharge from the leakage effect of such floating nodes may thus cause the occurrence of irreversible structural damages.